发明名称 |
Dummy flip chip bumps for reducing stress |
摘要 |
A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. |
申请公布号 |
US9287234(B2) |
申请公布日期 |
2016.03.15 |
申请号 |
US201414491309 |
申请日期 |
2014.09.19 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Wu Sheng-Yu;Kuo Tin-Hao;Chuang Chita;Chen Chen-Shien |
分类号 |
H01L23/00;H01L21/56;H01L23/31;H01L23/522;H01L23/532;H01L23/58;H01L21/60 |
主分类号 |
H01L23/00 |
代理机构 |
Slater & Matsil, L.L.P. |
代理人 |
Slater & Matsil, L.L.P. |
主权项 |
1. A method comprising:
forming a first package component comprising:
forming a first dielectric layer; andforming a dummy bump over the first dielectric layer, with an entirety of a bottom surface of the dummy bump contacting a top surface of the first dielectric layer; and bonding a second package component to the first package component, with the dummy bump in contact with the second package component, wherein after the bonding, a top surface of the dummy bump is in contact with a second dielectric layer in the second package component, with the first dielectric layer and the second dielectric layer contacting opposite surfaces of the dummy bump. |
地址 |
Hsin-Chu TW |