Semiconductor constructions

摘要

Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some embodiments may include a method in which a semiconductor substrate is provided to have a plurality of active area locations. Floating gates are formed over the active area locations, with the floating gates having widths that are entirely sub-lithographic. Adjacent floating gates are spaced from one another by gaps. Dielectric material and control gate material are formed over the floating gates and within the gaps. Some embodiments may include a construction in which a pair of adjacent floating gates are over a pair of adjacent active areas, with the floating gates being spaced from one another by a distance which is greater than a distance that the active areas are spaced from one another.

主权项

1. A pair of adjacent non-volatile memory cells comprising active areas separated by an isolation region, and floating gates over the active areas, the floating gates being shaped as vertically-extending pillars having a vertical height that is greater than a width of the pillars and being spaced from one another by a greater distance than the active areas are spaced from one another; the vertically-extending pillars consisting of a rectangular shape and comprising a single material; individual of the vertically-extending pillars having a completely planar horizontal lower surface that extends an entire width of the pillar which directly contacts gate dielectric material and a completely planar horizontal upper surface directly contacting another dielectric material; the rectangular vertically-extending pillars having vertical sidewalls that join to the upper and lower surfaces at 90° corners, the vertically extending pillars having insulative spacers along opposing vertical sidewalls, the insulative spacers consisting of a rectangular shape and covering less than a full height of the opposing vertical sidewalls with the insulative spacers and the isolation region having coplanar upper surfaces, the gate dielectric extending beneath an entirety of a width of the insulative spacers.