Memory system and method using partial ECC to achieve low power refresh and fast access to data

摘要

A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

主权项

1. A method comprising:
while in a first mode:
refreshing a first set of memory cells of an array of a semiconductor device at a first rate, wherein a first type of data is stored in the first set of memory cells;refreshing a second set of memory cells of the array at a second rate that is greater than the first rate, wherein a second type of data is stored in the second set of memory cells; andcorrecting errors in the first type of data stored at the first set of the memory cells; and while in a second mode:
refreshing the first set of memory cells and the second set of memory cells at the second rate.