METHOD OF DECOMPOSING LAYOUT FOR QUADRUPLE PATTERNING TECHNOLOGY PROCESS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

摘要

A layout separation method for a quadruple patterning technology (QPT) process comprises: generating a first temporary pattern including rectangular features and a second temporary pattern including cross couple features by separating the rectangular features in a rectangular shape and the cross couple features in a Z shape in a layout of a semiconductor device; generating a third temporary pattern and a fourth temporary pattern by performing a pattern separation operation on the first temporary pattern in a first direction; generating a first target pattern and a second target pattern by merging each of the cross features included in the second temporary pattern with one from the third temporary pattern and the fourth temporary pattern; and generating first to fourth separation patterns by performing the pattern separation operation on the first target pattern and the second target pattern in a second direction.