| 发明名称 |
SELECTIVELY REDUCING GRAPH BASED ANALYSIS PESSIMISM |
| 摘要 |
A method, system or computer usable program product for improving a circuit design having a set of endpoint circuits including identifying a subset of the set of endpoint circuits for further timing analysis based on graph based analysis (GBA) of the circuit design; performing path based analysis (PBA) of a set of endpoint circuit paths in the subset of endpoint circuits; and providing a timing margin between graph based analysis and path based analysis for each of the set of endpoint circuit paths for reducing pessimism in subsequent graph based analysis of the set of endpoint circuit paths. |
| 申请公布号 |
US2016070844(A1) |
申请公布日期 |
2016.03.10 |
| 申请号 |
US201414480543 |
申请日期 |
2014.09.08 |
| 申请人 |
Synopsys Inc. |
发明人 |
Shyamsukha Ritesh;Feng Chunyang;Radhakrishnan Shankar;Craven Ted L. |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of improving a circuit design having a set of endpoint circuits comprising:
identifying a subset of the set of endpoint circuits for further timing analysis based on graph based analysis (GBA) of the circuit design; performing path based analysis (PBA) of a set of endpoint circuit paths in the subset of endpoint circuits; and providing a timing margin between graph based analysis and path based analysis for each of the set of endpoint circuit paths for reducing pessimism in subsequent graph based analysis of the set of endpoint circuit paths. |
| 地址 |
Mountain View CA US |
