CYCLE-ACCURATE REPLAY AND DEBUGGING OF RUNNING FPGA SYSTEMS

摘要

As described herein, a tool records a log (or trace) of all sources of non-determinism in the system. In most of the cases, it's enough to log all transitions and the exact timestamps at all the entry and exit points of the system. By using this information it is possible to recreate a cycle accurate execution of the hardware system in simulation. Unlike CHIPSCOPE and SIGNALTAP which let you monitor a small number of signals in the design, the tool provides visibility into the whole system.

主权项

1. A method for analyzing a hardware circuit implemented in a field-programmable gate array (FPGA), the method comprising:
receiving by a computer a log from the FPGA, the log indicating a plurality of events that occurred in the FPGA and respective timestamps associated with the events; utilizing, by the computer, the log to replay a prior FPGA execution in a simulation, wherein the replay is based upon non-deterministic input data and timing information in the log, and wherein the replay is performed using a hardware description language (HDL) code which is the same as that used to configure the FPGA after synthesis; and outputting, by the computer, the simulation.