| 摘要 |
According to one embodiment, a semiconductor memory device includes a source voltage adjustment circuit and a word line voltage adjustment circuit, which are configured to respectively supply a source voltage supply end and a word line switchingly with voltage-adjusted voltages, in response to a mode switching signal for switching between a retention state mode and an active state mode, wherein the source voltage supply end is connected to sources of MOS transistors forming a flip-flop of a memory cell, and the word line is connected to gates of access transistors. |
| 主权项 |
1. A semiconductor memory device comprising:
a first MOS transistor including a source, a drain, and a gate, such that its source is connected to a first bit line and its gate is connected to a word line; a second MOS transistor including a source, a drain, and a gate, such that its source is connected to a second bit line and its gate is connected to the word line; a third MOS transistor including a source, a drain, and a gate, such that its source is connected to a source voltage supply end, its gate is connected to the drain of the second MOS transistor, and its drain is connected to the drain of the first MOS transistor; a fourth MOS transistor including a source, a drain, and a gate, such that its source is connected to the source voltage supply end, its gate is connected to the drain of the first MOS transistor, and its drain is connected to the drain of the second MOS transistor; a source voltage adjustment circuit configured to supply the source voltage supply end switchingly with a first voltage and a second voltage that has been obtained by adjusting the first voltage by a predetermined voltage, in response to a mode switching signal for switching between a retention state mode where data retention is performed and an active state mode where read or write of data is performed; and a word line voltage adjustment circuit configured to supply the word line switchingly with application voltages between a third voltage and a fourth voltage that has been obtained by adjusting the third voltage by a predetermined voltage, in response to the mode switching signal. |
