发明名称 CACHE UNIT AND PROCESSOR
摘要 According to an embodiment, a cache unit includes: a first memory configured to temporarily hold data and an address of the data, a second memory configured to temporarily hold an address of particular data set in advance, and a controller configured to, when an instruction to load the data is made for a first specified address, search for a storage destination of the first specified address, output the data of the first specified address if the storage destination is the first memory, and output the particular data if the storage destination is the second memory.
申请公布号 US2016070649(A1) 申请公布日期 2016.03.10
申请号 US201514641827 申请日期 2015.03.09
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MAEDA Seiji
分类号 G06F12/08;G06F12/12 主分类号 G06F12/08
代理机构 代理人
主权项 1. A cache unit comprising: a first memory configured to temporarily hold data and an address of the data; a second memory configured to temporarily hold an address of particular data set in advance; and a controller configured to, when an instruction to load the data is made for a first specified address, search for a storage destination of the first specified address, output the data of the first specified address if the storage destination is the first memory, and output the particular data if the storage destination is the second memory.
地址 Tokyo JP