DEVICE AND METHOD FOR STORING DATA IN A PLURALITY OF MULTI-LEVEL CELL MEMORY CHIPS

摘要

A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips.

主权项

1. A device for storing data in a plurality of multi-level cell memory chips, each of the multi-level cell memory chips having a plurality of memory cells, each memory cell having a plurality of programmable levels, the device comprising:
a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of the generated candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the plurality of candidate scrambled sequences of data based on the results of the calculated cost functions; and a storing unit to store the selected candidate scrambled sequence of data in the plurality of multi-level cell memory chips by storing the subsequences of the selected candidate scrambled sequence across the plurality of multi-level memory chips.