| 摘要 |
A semiconductor device having a function of detecting abnormality of a frequency of a clock includes a PLL circuit configured to generate a clock signal of the semiconductor device, a delay circuit in which an amount of delay of an output signal with respect to an input signal is equal to an amount of delay at a critical path of the semiconductor device, a first selection circuit configured to select an input to the delay circuit between a first input that is derived from the clock signal and a second input, which is the output signal of the delay circuit, a frequency dividing circuit configured to divide a frequency of the output signal of the delay circuit, and a second selection circuit configured to select as an input to the PLL circuit one of a reference signal and an output of the frequency dividing circuit. |
