发明名称 C-ELEMENT WITH NON-VOLATILE BACK-UP
摘要 The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters (110, 112) cross-coupled between first and second complementary storage nodes ( Q, Z), the second storage node (Z) forming an output node of the C-element; and a non-volatile memory comprising: a first resistive element (202) having a first terminal coupled to the first storage node ( Q); a second resistive element (204) having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to have one of at least two resistive states (Rmin, Rmax), wherein a second terminal of the first resistive element (202) is coupled to a second terminal of the second resistive element (204) via a first transistor (210); and a control circuit (232).
申请公布号 US2016071587(A1) 申请公布日期 2016.03.10
申请号 US201514845213 申请日期 2015.09.03
申请人 Commissariat à I`énergie atomique et aux énergies alternatives ;Centre National de la Recherche Scientifique 发明人 Di Pendina Grégory;Beigne Edith;Zianbetov Eldar
分类号 G11C13/00;G11C11/22;G11C11/16 主分类号 G11C13/00
代理机构 代理人
主权项 1. A circuit comprising: a C-element having first and second input nodes and first and second inverters cross-coupled between first and second complementary storage nodes, the second storage node forming an output node of the C-element; and a non-volatile memory comprising: a first resistive element having a first terminal coupled to the first storage node;a second resistive element having a first terminal coupled to the second storage node, at least one of the first and second resistive elements being programmable to have one of at least two resistive states, a data value being represented by the relative resistances of the first and second resistive elements, wherein a second terminal of the first resistive element is coupled to a second terminal of the second resistive element via a first transistor; anda control circuit adapted, during a backup phase of a data bit stored at the first and second storage nodes to the non-volatile memory, to render conductive the first transistor while different logic levels are applied to the first and second input nodes of the C-element.
地址 Paris FR