DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE

摘要

A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed.

主权项

1. An integrated circuit test architecture comprising:
(a) cores of functional circuits; (b) test wrapper architectures, each test wrapper architecture being connected with one core; (c) test access mechanisms, each test access mechanisms being connected with one of the test wrapper architectures; (d) a test access mechanism controller having test access mechanism interface buses, each interface bus being connected with one of the test access mechanisms; and (e) double data rate circuitry, the double data rate circuitry having a double data rate parallel data bus input, a double data rate clock input, a clock output connected to the controller circuitry, a load instruction register output connected to the controller circuitry, mode outputs connected to the controller circuitry, and parallel data bus outputs connected to the controller circuitry and coupled to the functional circuitry.