| 摘要 |
In described examples of providing multiple clock frequencies for an integrated circuit having a plurality of modules, a reference clock signal (fin) is frequency division processed (401) to generate sub-divider outputs of fin divided by a plurality of different prime numbers, and by prime numbers raised to an integer power, to collectively provide a plurality of prime number-based clock signals that each have a frequency divider factor (divider factor) in a predetermined divider range. For at least a portion of other divider factors, two or more of the sub-divider outputs are combined (402) to generate additional clock signals that each provide an additional divider factor. A first module frequency selects (403) at least a first selected clock signal from the prime number-based clock signals and additional clock signals, and a second module frequency selects at least a second selected clock signal from the prime number-based clock signals and additional clock signals. |
