PROCESSOR AND DATA REARRANGEMENT METHOD

摘要

The present disclosure provides a processor that processes data for arithmetic operation configured from an arrangement of a plurality of data elements, the processor comprising: a plurality of registers that store data including the data for arithmetic operation; a command decoder that decodes a data rearrangement command designating at least one of the plurality of registers in which at least one piece of the data for arithmetic operation is stored; a plurality of data cut-out units that are provided in correspondence to the at least one piece of the data for arithmetic operation and that generate partial data by cutting out a predetermined number of data elements from the data for arithmetic operation stored in a register designated by the data rearrangement command; and a data linking unit that links a plurality of pieces of partial data generated by the plurality of data cut-out units. The plurality of data cut-out units cut out the predetermined number of data elements from corresponding data for arithmetic operation at positions that are designated by the data rearrangement command and that are identical in the data for arithmetic operation. The operation of the plurality of data cut-out units generating the partial data by cutting out the predetermined number of data elements, and the operation of the data linking unit linking the plurality of pieces of partial data are executed in response to the decoding of a single data rearrangement command by the command decoder.