发明名称 SEMICONDUCTOR DEVICE
摘要 A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of kinds of circuits and transistors whose electrical characteristics are different between the circuits is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes an oxide semiconductor, a conductor, a first insulator, a second insulator, and a third insulator. The conductor has a region where the conductor and the oxide semiconductor overlap with each other. The first insulator is positioned between the conductor and the oxide semiconductor. The second insulator is positioned between the conductor and the first insulator. The third insulator is positioned between the conductor and the second insulator. The second insulator has a negatively charged region.
申请公布号 US2016071840(A1) 申请公布日期 2016.03.10
申请号 US201514841773 申请日期 2015.09.01
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 YAMAMOTO Yoshitaka;SAKAKURA Masayuki;TANAKA Tetsuhiro;MATSUBAYASHI Daisuke
分类号 H01L27/06;H01L29/786;H01L49/02;H01L23/50 主分类号 H01L27/06
代理机构 代理人
主权项 1. A semiconductor device comprising: a first circuit; a second circuit; and a third circuit, wherein the first circuit comprises a first transistor, a first capacitor, and a first wiring, wherein the first transistor comprises a first conductor and a first oxide semiconductor, wherein the first conductor comprises a region in contact with the first oxide semiconductor, wherein one terminal of the first capacitor is electrically connected to the first conductor, wherein the other terminal of the first capacitor is electrically connected to the first wiring, wherein the second circuit comprises a second transistor, a second capacitor, and a second wiring, wherein the second transistor comprises a second conductor and a second oxide semiconductor, wherein the second conductor comprises a region in contact with the second oxide semiconductor, wherein one terminal of the second capacitor is electrically connected to the second conductor, wherein the other terminal of the second capacitor is electrically connected to the second wiring, wherein the third circuit comprises a third transistor, wherein the third transistor comprises a third conductor, a third oxide semiconductor, a first insulator, a second insulator, and a third insulator, wherein the third conductor and the third oxide semiconductor overlap with each other, wherein the first insulator is positioned between the third conductor and the third oxide semiconductor, wherein the second insulator is positioned between the third conductor and the first insulator, wherein the third insulator is positioned between the third conductor and the second insulator, wherein the second insulator comprises an electron trap region, wherein a gate voltage at which a drain current in a subthreshold region is 1×10−12 A is greater than or equal to 0.8 V and less than or equal to 1.5 V in the first transistor, and wherein a gate voltage at which a drain current in a subthreshold region is 1×10−12 A is greater than or equal to 0 V and less than or equal to 0.7 V in the second transistor.
地址 Atsugi-shi JP