SHARED DIVIDE BY N CLOCK DIVIDER

摘要

A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division processed to generate sub-divider outputs of fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals that each have a frequency divider factor (divider factor) in a predetermined divider range. For at least a portion of other divider factors, two or more of the sub-divider outputs are combined to generate additional clock signals that each provide an additional divider factor. A first module frequency selects at least a first selected clock signal from the prime number-based clock signals and additional clock signals, and a second module frequency selects at least a second selected clock signal from the prime number-based clock signals and additional clock signals.

主权项

1. A method of providing multiple clock frequencies for an integrated circuit (IC) including a plurality of modules, comprising:
frequency division processing of at least one reference clock signal (fin) to generate sub-divider outputs of said fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals each providing a frequency divider factor (divider factor) in a predetermined divider range including at least one divider factor that is not equal to 2N, and for at least a portion of others of said divider factors that are not said prime numbers or said prime numbers raised to an integer power, combining combinations of two or more of said sub-divider outputs to generate additional clock signals that each provide an additional divider factor; a first of said plurality of modules frequency selecting at least a first selected clock signal from said plurality of prime number-based clock signals and said additional clock signals, and a second of said plurality of modules-frequency selecting at least a second selected clock signal from said plurality of prime number-based clock signals and said additional clock signals.