发明名称 METHOD FOR BIASING AN EMBEDDED SOURCE PLANE OF A NON-VOLATILE MEMORY HAVING VERTICAL SELECT GATES
摘要 A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a state control gate, in series with a select transistor that includes a vertical select control gate, common to the twin memory cells, and a source connected to an embedded source line, common to the memory cells. The drains of the floating-gate transistors of the twin memory cells are connected to a same bit line. The method includes controlling a memory cell so as to turn it on to couple the source line to a bit line coupled to the ground, during a step of programming or reading another memory cell.
申请公布号 US2016071598(A1) 申请公布日期 2016.03.10
申请号 US201514810283 申请日期 2015.07.27
申请人 STMicroelectronics ( Rousset ) SAS 发明人 La Rosa Francesco;Niel Stephan;Regnier Arnaud
分类号 G11C16/10;G11C16/04;G11C16/26 主分类号 G11C16/10
代理机构 代理人
主权项 1. A method comprising: controlling a non-volatile memory on a semiconductor substrate, the memory including: bit lines,control gate lines,a source line formed deep down in the substrate, andpairs of twin memory cells, each including a first memory cell that includes a first floating-gate transistor having a control gate coupled to a first one of the control gate lines, a first conduction terminal coupled to a first one of the bit lines and a second conduction terminal coupled to the source line through a first select transistor having an embedded vertical select control gate, coupled to the word line, and a second memory cell that includes a second floating-gate transistor having a control gate coupled to a second one of the control gate lines, a first conduction terminal coupled to the first bit line and a second conduction terminal coupled to the source line through a second select transistor sharing with the first select transistor the select control gate, wherein the controlling includes: turning on a first selected memory cell of one of the pairs of memory cells, thereby electrically coupling the source line to a line coupled to ground, programming or reading a second selected memory cell of the pairs of memory cells while the first selected memory cell electrically couples the source line to the line coupled to ground.
地址 Rousset FR