CMOS FABRICATION

摘要

A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.

主权项

1. A method of fabricating a portion of a DRAM, the method comprising:
providing a substrate; defining an nMOS region and a pMOS region within the substrate; masking the pMOS region with a pMOS mask; doping gate, source and drain regions within the nMOS region while the pMOS mask covers the pMOS region; doping the nMOS region with lightly doped drain (LDD) and Halo implants while the pMOS mask covers the pMOS region; removing the pMOS mask; masking the nMOS region with an nMOS mask; doping gate, source and drain regions within the pMOS region while the nMOS mask covers the nMOS region; and doping the pMOS region with LDD and Halo implants while the nMOS mask covers the nMOS region.