发明名称 ヘテロジニアスメモリアクセス
摘要 A memory controller operable for selective memory access to areas of memory exhibiting different attributes leverages different memory capabilities that vary access speed, retention time and power consumption, among others. Different areas of memory have different attributes while remaining available to applications as a single contiguous range of addressable memory. The memory controller employs an operating mode that identifies operational priorities for a computing device, such as speed, power conservation, or efficiency. The memory controller identifies an area of memory based on an expected usage of the data stored in the area, for example an access frequency indicating future retrieval. The memory controller therefore selects areas of memory based on the operating mode and the expected usage of data to be stored in the area according to a heuristic that favors areas of memory based on those exhibiting attributes having a high correspondence to the expected usage of the data.
申请公布号 JP5883089(B2) 申请公布日期 2016.03.09
申请号 JP20140166408 申请日期 2014.08.19
申请人 インテル・コーポレーション 发明人 サラスワット、ルチル;グリース、マティアス;カウリー、ニコラス ピー.
分类号 G06F12/06 主分类号 G06F12/06
代理机构 代理人
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