| 摘要 |
A current latched sense amplifier CSLA 103 comprising a reference current input terminal (109), a control line input terminal 125, a sense current input terminal 108, an output terminal 106, a first NAND gate 100, a transmission gate 104, and two cross coupled inverters T1, T2, T3, T4 each comprising an nMOSFET device T2, T4. The first NAND gate 100 comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate 104 comprises two transmission terminals and a gate terminal which is coupled to the control line terminal 125. Sources of the n-MOSFETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively. The gate terminal of the transmission gate allows for on/off switching. A first inverter 102 couples one of the input terminals of the first NAND gate to the control line 125. A second NAND gate may be coupled to the second terminal of the amplifier, having a second input controlled by the output of the inverter 102. An electronic circuit may also be included which comprises static memory cells and the current sense amplifier (or current latched sense amplifier). Static Memory Cells may be arranged (figure 4 or 5) such that the data output of each of the cells is coupled via an nMOSFET stack (116 Figure 4) to the sense input of the current sense amplifier. |
