发明名称 集積回路内の組み込みメモリおよび専用プロセッサ構造
摘要 An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory processor can be hardwired and dedicated to perform operations in the RAM element of the block random access memory.
申请公布号 JP5878639(B2) 申请公布日期 2016.03.08
申请号 JP20140539943 申请日期 2012.08.17
申请人 ザイリンクス インコーポレイテッドXILINX INCORPORATED 发明人 ニーリー,クリストファー・イー;ブレブナー,ゴードン・ジェイ
分类号 G06F15/82;G06F12/00;H03K19/173 主分类号 G06F15/82
代理机构 代理人
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