发明名称 Resistive memory write circuitry with bit line drive strength based on storage cell line resistance
摘要 An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.
申请公布号 US9281043(B1) 申请公布日期 2016.03.08
申请号 US201414582745 申请日期 2014.12.24
申请人 Intel Corporation 发明人 Jain Pulkit;Hamzaoglu Fatih;Wei Liqiong
分类号 G11C11/00;G11C11/16;G06F12/02;G06F3/06 主分类号 G11C11/00
代理机构 Blakely, Sokoloff, Taylor & Zafman LLP 代理人 Blakely, Sokoloff, Taylor & Zafman LLP
主权项 1. An apparatus, comprising: a bit line; first and second storage cells coupled to said bit line, said first storage cell having a first access transistor, said first access transistor coupled to a first line resistance, said second storage cell having a second access transistor, said second access transistor coupled to a second line resistance, said second line resistance being greater than said first line resistance; first and second drivers coupled to said bit line, said second driver being a stronger driver than said first driver; circuitry to select said first driver to write information into said first storage cell and select said second driver to write information into said second storage cell.
地址 Santa Clara CA US