Methods, systems, and apparatus for clock topology planning with reduced power consumption

摘要

In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.

主权项

1. A method for optimizing power consumption in a clock tree network, the method comprising:
receiving a netlist of an integrated circuit design without prior knowledge of signals that may be used to disable clock signals; analyzing the netlist of the integrated circuit design to determine one or more feasible disable signals that can be used to disable clock signals that are coupled into synchronous circuit elements; grouping synchronous circuit elements together in response to the one or more feasible disable signals to determine if one or more clock subtrees having branches of balanced insertion delay can be formed to reduce power consumption when clock signals are disabled by the one or more feasible disable signals; and selecting to implement within a clock tree plan one clock subtree with the least power consumption with clock gates disabled by the one or more feasible disable signals, provided that one or more timing constraints are satisfied; wherein the receiving, analyzing, grouping, and selecting are implemented by a processor executing instructions.