Semiconductor integrated circuit capable of controlling read command

摘要

The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

主权项

1. A semiconductor integrated circuit comprising:
a command decoder configured to provide a read command in synchronization with a second edge of a clock according to an external command in synchronization with a first edge of the clock having first and second edges; a read/write command controller configured to provide a read clock in synchronization with the second edge of the clock in response to the read command; a column address latch unit configured to latch an external address in response to the read command, and provide a column address in synchronization with the second edge of the clock; and a column command generator configured to provide a write-read command for generating the read clock in response to the read command.