发明名称 Data processing device
摘要 A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.
申请公布号 US9280341(B2) 申请公布日期 2016.03.08
申请号 US201314144822 申请日期 2013.12.31
申请人 RENESAS ELECTRONICS CORPORATION 发明人 Ohtani Sugako;Kondo Hiroyuki
分类号 G06F9/30;G06F9/32 主分类号 G06F9/30
代理机构 Buchanan Ingersoll & Rooney PC 代理人 Buchanan Ingersoll & Rooney PC
主权项 1. A data processing device comprising: an instruction decoder for decoding an instruction code in an arithmetic instruction; a controller for detecting an effective data width of operation data to be processed for the arithmetic instruction, for detecting data type information specifying whether or not the operation data include a sign, and, based on the decode result from the instruction decoder, for determining an instruction execution cycle number which is the number of cycles of execution of the arithmetic instruction corresponding to the detected effective data width and the data type information; and an arithmetic operation unit for executing the arithmetic instruction with the number of cycles for the instruction execution determined by the controller.
地址 Kawasaki-Shi, Kanagawa JP