Semiconductor device including plural chips stacked to each other

摘要

A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal. A read clock signal is provided to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address. The one DRAM device delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate. First delayed read clock and second delayed read clock signals are provided. The read data is received on the data bus in synchronization with the second delayed read clock signal.

主权项

1. A semiconductor device comprising:
a plurality of stacked core chips, each core chip including a memory cell array, a data terminal, and an output circuit configured to output read data read from the memory cell array to the data terminal; and an interface chip that configured to control the core chips, wherein the data terminals of the core chips are commonly connected to each other to form a data path common to the core chips, the output circuits are activated in response to a first read clock signal supplied from the interface chip, and the interface chip receives the read data through the data path, wherein the interface chip comprises:
a first counter circuit that updates a first count value based on the first read clock signal;a second counter circuit that updates a second count value based on a signal generated by delaying the first read clock signal; anda FIFO circuit that latches the read data sequentially supplied through the data path and sequentially outputs the read data, the FIFO circuit including a plurality of input circuits, each having an input node and an output node, and a plurality of output circuits, each having an input node and an output node, wherein the input nodes of the input circuits are commonly connected to the data path, the input nodes of the output circuits are each connected to a corresponding one of the output nodes of the input circuits, and the output nodes of the output circuits are connected in common, and wherein the FIFO circuit is configured so that any one of the input circuits of the FIFO circuit can be activated based on the first count value and any one of the output circuits of the FIFO circuit can be activated based on the second count value.