| 摘要 |
A shift register includes series-connection circuits to transmit a shift pulse. The series-connection circuits include a continuous stage group with continuous stages. Each stage of the continuous stage group includes a first output transistor, a first capacitor, an input gate, a first switching element, a second switching element, a third switching element, and a fourth switching element. |
| 主权项 |
1. A shift register, including one or more series-connection circuits in each of which stages are series-connected with each other to transmit a shift pulse,
at least one of said one or more series-connection circuits including, among all stages thereof, a continuous stage group consisting of a plurality of continuous stages, each stage of the continuous stage group comprising: a first output transistor, having (i) a drain to which a first direct voltage is applied and (ii) a source serving as a first output terminal which is an output terminal of said each stage; a first capacitor, having one end connected with a gate of the first output transistor; an input gate, to which a shift pulse for said each stage is input and via which a potential to be supplied to said one end of the first capacitor is transmitted during a pulse period of the shift Pulse for said each stage; a first switching element, having (i) one end connected with the other end of the first capacitor, (ii) the other end to which the first direct voltage is applied, and (iii) a conduction and blocking control terminal, to which a first clock signal corresponding to said each stage is input, an active clock pulse period of the first clock signal not overlapping the pulse period of the shift pulse for said each stage; a second switching element, having (i) one end connected with the other end of the first capacitor, (ii) the other end to which a second direct voltage lower than the first direct voltage is applied, and (iii) a conduction and blocking control terminal to which a shift pulse for said each stage is input; a third switching element, having (i) one end connected with said one end of the first capacitor, (ii) the other end to which the second direct voltage is applied, and (iii) a conduction and blocking control terminal to which a pulse signal from an output terminal of a first predetermined other stage included in one of said one or more series-connection circuits is input, a phase of the pulse signal being retarded with respect to that of a shift pulse outputted from said each stage; and a fourth switching element, having (i) one end connected with the first output terminal, (ii) the other end to which the second direct voltage is applied, and (iii) a conduction and blocking control terminal to which a first conduction and blocking control signal corresponding to said each stage is input, an active period of the first conduction and blocking control signal not overlapping the active clock pulse period of the first clock signal. |
