Controlling timing of negative charge injection to generate reliable negative bitline voltage

摘要

Embodiments relate to preventing or mitigating excessive drop in the negative voltage level of a bitline of memory bitcells by controlling the delay of a trigger signal for initiating injection of negative charge into the bitline. A write assist circuit causes negative charge to drop gradually in response to receiving a data input indicating a negative value of the bitline. When supply voltage is high, the timed delay of trigger signal is reduced, thereby causing negative charge to be injected into the bitline while bitline voltage remains at a higher voltage level and before the bitline voltage drops close to ground voltage. Since the negative charge is injected while the bitline voltage level is relatively high, the bitline is prevented from being pulled down to an excessively negative voltage level even when the supply voltage is relatively high.

主权项

1. A memory device, comprising:
a plurality of memory bitcells arranged in columns and rows, each column of the bitcells connected by a pair of bitlines; a write assist circuit connected to at least one pair of the bitlines and configured to inject negative charge to a bitline of the pair of the bitlines to place the bitline in a negative voltage level in a write operation; a column decoder configured to generate a column select signal indicating a column of the bitcells for the write operation, delay of the column select signal changing at a first rate responsive to change in a supply voltage level of the memory device; and a trigger signal generator configured to generate a trigger signal to set time for injecting negative charge into the bitline to place the bitline in the negative voltage level, delay of the trigger signal changing at a second rate higher than the first rate responsive to change in the supply voltage level.