发明名称 Memory sense amplifier and column pre-charger
摘要 A memory includes a number of storage elements connected to a pair of bit-lines, a bit-line pre-charging circuit, a sense amplifier connected to the pair of bit-lines through a column-select switch, a transition detection circuit connected to an output of the sense amplifier, and a local pre-charge control circuit connected to the transition detection circuit and having a local pre-charge control signal output connected to the bit-line pre-charging circuit.
申请公布号 US9281055(B2) 申请公布日期 2016.03.08
申请号 US201414217609 申请日期 2014.03.18
申请人 AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. 发明人 Sahu Rahul;Rai Dharmendra Kumar
分类号 G11C11/419;G11C11/4091;G11C7/12 主分类号 G11C11/419
代理机构 Hamilton DeSanctis & Cha 代理人 Hamilton DeSanctis & Cha
主权项 1. A memory comprising: a plurality of storage elements connected to a pair of bit-lines; a bit-line pre-charging circuit; a sense amplifier connected to the pair of bit-lines through a column-select switch; a transition detection circuit connected to an output of the sense amplifier yielding a transition detected signal; and a local pre-charge control circuit comprising a first input receiving the transition detected signal, and a second input receiving a global pre-charge signal, the local pre-charge control circuit comprising an output yielding a local pre-charge control signal, wherein the output of the local pre-charge control circuit is connected to the bit-line pre-charging circuit, and wherein the local pre-charge control circuit is operable to assert the output of the local pre-charge control circuit based on both the global pre-charge signal and the transition detected signal being in an asserted state.
地址 Singapore SG