Storage medium and accessing system utilizing the same

摘要

A storage medium communicating with a memory controller sent a read command is disclosed. The storage medium includes a plurality of memory units. Each memory unit includes at least sixteen memory cells coupled to a word line and a plurality of bit lines. A controlling unit receives first address information according to the read command and generates a row read signal and a column read signal according to the first address information. A row decoding unit activates the word line according to the row read signal. A column decoding unit activates the bit lines according to the column read signal to output a plurality of storing bits stored in the sixteen memory cells. A read-out unit processes the storing bits to generate a plurality of reading bits. The controlling unit outputs the reading bits to the memory controller in serial.

主权项

1. A storage medium for communicating with a memory controller sent a read command, comprising:
a plurality of memory units, each comprising at least sixteen memory cells coupled to a word line and a plurality of bit lines; a controlling unit comprising a SPI command control logic circuit and receiving first address information according to the read command and generating a row read signal and a column read signal according to the first address information; a row decoding unit activating the word line according to the row read signal; a column decoding unit activating the bit lines according to the column read signal to output a plurality of storing bits stored in the sixteen memory cells; and a read-out unit processing the storing bits to generate a plurality of reading bits, wherein the controlling unit outputs the reading bits to the memory controller in serial, wherein the column decoding unit activates at least sixteen bit lines to access one of the memory units every time so as to make the storage medium to output at least sixteen bits for each first address information; and wherein the storage medium communicates with the memory controller via a serial peripheral interface, and the serial peripheral interface utilizes only six pins for transmitting a clock signal, a chip select signal, command packages, the first address information and data packages.