| 发明名称 | Content addressable memory | ||
| 摘要 | A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot. | ||
| 申请公布号 | US9280633(B2) | 申请公布日期 | 2016.03.08 |
| 申请号 | US201414279406 | 申请日期 | 2014.05.16 |
| 申请人 | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 发明人 | Kim Young Seog;Hsu Kuoyuan;Chang Jacklyn |
| 分类号 | G11C15/00;G06F17/50;G11C15/04;H03K19/20 | 主分类号 | G11C15/00 |
| 代理机构 | Hauptman Ham, LLP | 代理人 | Hauptman Ham, LLP |
| 主权项 | 1. A method of designing a content-addressable memory (CAM), the method comprising: associating a plurality of CAM cells with a summary circuit; the summary circuit comprising: a first level of logic gates having inputs, each input receiving an output of a CAM cell; anda second level of logic gates having inputs, each input receiving an output of one gate of the first level of logic gates; and selecting logic gates in at least one of the first level of logic gates or the second level of logic gates to have an odd number of input pins, an input pin of a selected logic gate and an output pin of the selected logic gate sharing a layout sub-slot. | ||
| 地址 | TW | ||