| 主权项 |
1. A method of fabricating a semiconductor device comprising:
providing a substrate having a surface comprising silicon, the surface having formed therein a plurality of device regions comprising a first active region for a SRAM device, a second active region for the SRAM device, a third active region for a logic device, and a fourth active region for the logic device, the first active region comprising a first substantially undoped layer at the surface and a first highly doped p-type conductivity screening layer beneath the first substantially undoped layer, the second active region comprising a second substantially undoped layer at the surface and a second highly doped n-type conductivity screening layer beneath the second substantially undoped layer, the third active region comprising a doped p-type conductivity region extending from the surface, and the fourth active region comprising a layer of an alloy of silicon and germanium at the surface and a doped n-type conductivity region beneath the layer of the alloy of silicon and germanium, forming one of a first gate stack or a second gate stack in each of the first active region, the second active region, the third active region, and the fourth active region, wherein the first gate stack comprises at least one gate dielectric layer and at least one metal layer, and wherein the second gate stack comprises at least one gate dielectric layer, and at least one metal layer, wherein each of first and second gate stacks are of substantially mid-gap workfunctions. |
