Stub minimization using duplicate sets of signal terminals having modulo-x symmetry in assemblies without wirebonds to package substrate

摘要

A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

主权项

1. A microelectronic: package, comprising:
a microelectronic element having a face and a plurality of element contacts thereon, the microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function; a substrate having first and second opposed surfaces, the substrate having a set of substrate contacts on the first surface facing the element contacts of the microelectronic element and joined to the element contacts; and a plurality of terminals at the second surface configured for connecting the microelectronic package with at least one component external to the package, the terminals electrically coupled with the substrate contacts and including first and second groups of data terminals, each of the first and second groups having at least eight data terminals disposed on first and second opposite sides of an axis, respectively, wherein each of the data terminals of the first and second groups are configured to carry data signals for read and write access to random access addressable memory locations of a memory storage array within the microelectronic element, and the data terminals of the first group have modulo-X symmetry about the axis with the second group of the data terminals, wherein X is an integer.