Circuits using gate-all-around technology

摘要

A semiconductor structure includes a first gate-all-around (GAA) structure configured to form a first circuit and a second GAA structure configured to form a second circuit similar to the first circuit. The first GAA structure and the second GAA structure have a same of at least one of the following exemplary features: a number of GAA devices in which current flows from a first oxide definition (OD) region to a second OD region; a number of GAA devices in which current flows from the second OD region to the first OD region; a number of first OD region contact elements; a number of second OD region contact elements.

主权项

1. A semiconductor structure, comprising:
a first gate-all-around (GAA) structure configured to form a first circuit; a second GAA structure configured to form a second circuit similar to the first circuit; wherein
each of the first GAA structure and the second GAA structure comprises:
at least one GAA device, each GAA device comprising:
at least one nanowire;a first oxide diffusion (OD) region and a second OD region connected to opposite ends of the at least one nanowire; anda gate region wrapping all around a portion of each of the at least one nanowire;at least one first OD region contact element, each first OD region contact element electrically coupled to a corresponding first OD region of the at least one GAA device; andat least one second OD region contact element, each second OD region contact element electrically coupled to a corresponding second OD region of the at least one GAA device; andthe first GAA structure and the second GAA structure have substantially a same of at least one of the following features:
a number of GAA devices in the at least one GAA device configured to have current flows from the first OD region to the second OD region;a number of GAA devices in the at least one GAA device configured to have current flows from the second OD region to the first OD region;a number of integral first OD region of the at least one GAA device;a number of integral second OD region of the at least one GAA device;an orientation of and a corresponding direction of current flow through the first GAA structure or the second GAA structure;a number of the at least one first OD region contact element;an orientation of the at least one first OD region contact element;a number of the at least one second OD region contact element;an orientation of the at least one second OD region contact element;a number of the at least one nanowire for each corresponding GAA devices of the first GAA structure and the second GAA structure;a number of rows of the at least one nanowire arranged in an array for each corresponding GAA devices of the first GAA structure and the second GAA structure;a number of nanowires in a row of the at least one nanowire arranged in the array for each corresponding GAA devices of the first GAA structure and the second GAA structure;a number of columns of the at least one nanowire arranged in the array for each corresponding GAA devices of the first GAA structure and the second GAA structure;a number of nanowires in a column of the at least one nanowire arranged in the array for each corresponding GAA devices of the first GAA structure and the second GAA structure; anda shape of the at least one nanowire for each corresponding GAA devices of the first GAA structure and the second GAA structure.