System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof

摘要

System-in-Packages (SiPs) and methods for producing SiPs are provided. In one embodiment, the above-described SiP fabrication method includes the step or process of forming a through-hole in a core package, the core package containing an electrically-conducive routing feature exposed at a sidewall surface of the through-hole. A leaded component is positioned adjacent the core package such that an elongated lead of the leaded component extends into the through-hole. An electrically-conductive material, such as solder, is then applied into the through hole to electrically couple the elongated lead of the leaded component to the electrically-conductive routing feature of the core package.

主权项

1. A method for producing a System-in-Package, the method comprising:
providing a core package comprising a molded body, a semiconductor die embedded in the molded body, and one or more Redistribution Layers (RDLs) formed over a molded body; forming a through-hole in the core package, the through-hole having a first portion extending through the RDLs and having a second portion extending through the molded body; positioning a leaded component adjacent the core package such that an elongated lead of the leaded component extends into the through-hole; and applying an electrically-conductive material between the elongated lead of the leaded component and an interconnect line contained within a sole or an outermost metal level of the RDLs to electrically couple the leaded component and the semiconductor die, the electrically-conductive material applied in sufficient volume to at least partially fill the first portion of the through-hole formed through the RDLs, while preventing ingress of the electrically-conductive material into the second portion of the through-hole formed through the molded body.