主权项 |
1. A memory device, comprising:
a memory array comprising a first memory array area configured to store memory data and a second memory array area configured to store error correction code associated with the memory data; a data input circuit comprising a set of serial-in-parallel-out write data registers, the data input circuit being configured to receive serial input data in response to a write signal and a write address, the serial input data being shifted into the write data registers in response to a clock signal, the data input circuit configured to convert the serial input data stored in the write data registers into a set of parallel input data, the parallel input data being provided to the memory array to be written to the first memory array area; an error correction code (ECC) generation circuit configured to receive the set of the parallel input data and to generate an ECC data word associated with the set of parallel input data, the ECC data word being stored in the second memory array area; a read data register coupled to the first memory array area, the read data register storing a set of read out data retrieved from the first memory array area in response to a read signal and a read address, the set of read out data having the same number of data words as the set of parallel input data; an ECC logic circuit configured to receive an ECC data word associated with the set of read out data retrieved from the second memory array area, the ECC logic circuit configured to perform error checking and error correction on the set of read out data using the retrieved ECC data word; and a data output circuit comprising a parallel-in-serial-out buffer configured to receive the set of corrected read out data and to select an output data from the set of corrected read out data corresponding to the read address. |