Clock and data recovery with high jitter tolerance and fast phase locking

摘要

Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.

主权项

1. A circuit for recovering clock and data from a serial data input signal using clock phase signals, the data input signal containing a serial stream of data, the clock phase signals oscillating at a frequency that approximately matches a data rate of the data input signal, and the clock phase signals equally spaced in phase, the circuit comprising:
a phase sampler configured to sample values of clock phase signals on edges of a data input signal; a phase adjuster configured to evaluate the sampled values of the clock phase signals to determine the last of the clock phase signals to rise before a respective edge of the data input signal and determine a timing relationship between the data input signal and the clock phase signals utilizing the last of the clock phase signals to rise before the respective edge of the data input signal; a phase selector configured to produce a clock output signal using the clock phase signals based on the timing relationship between the data input signal and the clock phase signals determined by the phase adjuster; and a data sampler configured to produce a data output signal by sampling the data input signal on edges of the clock output signal.