| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock phase adjustment circuit capable of bringing a clock between chips into a constant phase relationship, in a semiconductor device of a multichip configuration.SOLUTION: The clock phase adjustment circuit is used in the semiconductor device of the multichip configuration. A master chip includes a master flag generation circuit for generating a master flag, changing from a non-active state to an active state only once, at a timing representing the phase of a master clock. A slave chip includes a skew detection circuit for detecting skew between the master clock and slave clock, on the basis of the master flag supplied from the master chip, and a slave flag changing from a non-active state to an active state only once, at a timing representing the phase of the slave clock, and outputting a skew set value, and a phase adjustment circuit for adjusting the phase of the slave clock, depending on the skew set value.SELECTED DRAWING: Figure 1 |
