发明名称 SEMICONDUCTOR MEMORY CELL AND DRIVER CIRCUITRY WITH GATE OXIDE FORMED SIMULTANEOUSLY
摘要 The present disclosure provides for semiconductor structures and methods for making semiconductor structures. In one embodiment, isolation regions are formed in a substrate, and wells are formed between the isolation regions. The wells include a first low voltage well and a second low voltage well in a logic region of the substrate, and a memory array well in an NVM region of the substrate. A first layer of oxide is formed over the first low voltage well and the memory array well, and a second layer of oxide is formed over the second low voltage well, the second layer being thinner than the first layer. Gates are formed over the wells, including a first gate over the first low voltage well, a second gate over the second low voltage well, and a memory cell gate over the memory array well. Source/drain extension regions are formed around the gates.
申请公布号 US2016064082(A1) 申请公布日期 2016.03.03
申请号 US201414470374 申请日期 2014.08.27
申请人 HONG CHEONG MIN;Akhter Tahmina;Muller Gilles J. 发明人 HONG CHEONG MIN;Akhter Tahmina;Muller Gilles J.
分类号 G11C16/04;H01L21/8234;H01L29/66;H01L21/265;G11C16/08;H01L29/78;H01L29/423;H01L21/3213;G11C16/24;H01L27/115;H01L29/788 主分类号 G11C16/04
代理机构 代理人
主权项 1. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a non-volatile memory (NVM) structure in an NVM region of the substrate, the method comprising: forming isolation regions in the substrate; forming wells between the isolation regions, wherein the wells comprise a first low voltage well and a second low voltage well in a logic region of the substrate, and a memory array well in the NVM region; forming a first layer of oxide over the first low voltage well and the memory array well; forming a second layer of oxide over the second low voltage well, wherein the second layer of oxide is thinner than the first layer of oxide; forming gates over the wells, wherein the gates comprise a first gate over the first low voltage well, the first gate including the first layer of oxide,a second gate over the second low voltage well, the second gate including the second layer of oxide, anda memory cell gate over the memory array well, the memory cell gate including the first layer of oxide; and forming source/drain extension regions around the gates.
地址 Austin TX US