| 发明名称 |
THREE-PORT BIT CELL HAVING INCREASED WIDTH |
| 摘要 |
An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (CPP) associated with the bit cell. For example, a bit cell may be a 3-port static random access memory (SRAM) bit cell that is compatible with self-aligned double patterning (SADP) processes and that can be manufactured using semiconductor manufacturing processes of less than 14 nanometers (nm). |
| 申请公布号 |
US2016064067(A1) |
申请公布日期 |
2016.03.03 |
| 申请号 |
US201414468976 |
申请日期 |
2014.08.26 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
Mojumder Niladri Narayan;Song Stanley Seungchul;Wang Zhongze;Yeap Choh Fei |
| 分类号 |
G11C11/419;H01L27/11;H01L21/768;H01L21/3213 |
主分类号 |
G11C11/419 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a first read port; a second read port; and a write port; wherein a width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (CPP) associated with the bit cell. |
| 地址 |
San Diego CA US |
