发明名称 |
CHROMA CACHE ARCHITECTURE IN BLOCK PROCESSING PIPELINES |
摘要 |
Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued. |
申请公布号 |
WO2016032765(A1) |
申请公布日期 |
2016.03.03 |
申请号 |
WO2015US45129 |
申请日期 |
2015.08.13 |
申请人 |
APPLE INC. |
发明人 |
COTE, GUY;BRATT, JOSEPH, P.;MILLET, TIMOTHY, J.;KONG, SHING, I.;CHENG, JOSEPH, J. |
分类号 |
H04N19/127;H04N19/186;H04N19/42;H04N19/433 |
主分类号 |
H04N19/127 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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