主权项 |
1. A sampling circuit comprising
a first latch disposed on an upstream side of a logic circuit, receiving a first input signal, outputting a first output signal to said logic circuit, and switching to an opaque state or a transparent state according to a first trigger signal generated by a reference clock and a control clock; a second latch disposed on a downstream side of said logic circuit, receiving a second input signal from said logic circuit, outputting a second output signal, and switching to an opaque state or a transparent state according to a second trigger signal generated by said reference clock and said control clock, wherein a state of said first latch is opposite to a state of said second latch; and a signal transition detector electrically connected with said logic circuit, and detecting whether said second input signal outputted by said logic circuit is incorrect, and outputting a corresponding said control clock. |