Method to Control the Common Drain of a Pair of Control Gates and to Improve Inter-Layer Dielectric (ILD) Filling Between the Control Gates

摘要

A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

主权项

1. A semiconductor structure for a split gate flash memory cell device, the semiconductor structure comprising:
a semiconductor substrate including a first source/drain region and a second source/drain region; a control gate and a memory gate spaced over the semiconductor substrate between the first and second source/drain regions; a charge trapping dielectric structure arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate; and a hard mask arranged over the control gate and including an asymmetric profile, the asymmetric profile tapering in height away from the memory gate.