ESD SNAPBACK BASED CLAMP FOR FINFET

摘要

There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

主权项

1. A field effect transistor configured as an ESD protection device, said field effect transistor comprising:
a semiconductor substrate; a gate formed on the substrate; a dummy gate formed on the substrate spaced apart from the gate; a source diffusion region formed in the substrate adjacent a first end of the gate; a first drain diffusion region formed in the substrate, the first drain diffusion region disposed intermediate of the gate and the dummy gate and adjacent to a second end of the gate and a first end of the dummy gate; a second drain diffusion region formed in the substrate, the second drain diffusion region spaced apart from the first drain diffusion region; and a contact electrically connected to the second drain diffusion region.