ADDRESS ALIGNER AND MEMORY DEVICE INCLUDING THE SAME

摘要

An address aligner includes a command address providing unit, an alignment signal providing unit and an alignment unit. The command address providing unit outputs a sync command address signal by delaying a command address signal in synchronization with a first clock signal. The sync command address signal is synchronized with the first clock signal. The alignment signal providing unit outputs alignment clock signals by delaying a chip select signal in synchronization with a second clock signal. The alignment clock signals are synchronized with the second clock signal. The alignment unit outputs a plurality of addresses in synchronization with the alignment clock signals. The plurality of addresses is included in the sync command address signal. If the address aligner according to example embodiments is used, the operation speed of the memory device may be increased by aligning a plurality of addresses in synchronization with the alignment clock signal that is generated based on a chip select signal.

主权项

1. An address aligner comprising:
a command address providing unit configured to output a sync command address signal by delaying a command address signal in synchronization with a first clock signal, the sync command address signal being synchronized with the first clock signal; an alignment signal providing unit configured to output alignment clock signals by delaying a chip select signal in synchronization with a second clock signal, the alignment clock signals being synchronized with the second clock signal; and an alignment unit configured to output a plurality of addresses in synchronization with the alignment clock signals, the plurality of addresses being included in the sync command address signal.