发明名称 |
SYSTEM AND METHOD FOR DYNAMICALLY MANAGED TASK SWITCH LOOKAHEAD |
摘要 |
A processing system includes a processor pipeline, a detector circuit, and a task scheduler. The detector circuit includes a basic block detector circuit to determine that the processor pipeline received a first instruction of a first instance of a basic block, and to determine that a last-in-order instruction of the first instance of the basic block is a resource switch instruction (RSWI), and an indicator circuit to provide an indication in response to determining that the processor pipeline received the first instruction of a second instance of the basic block. The task scheduler initiates a resource switch, in response to the indication, at a time subsequent to the first instruction being received that is based on a cycle count that indicates a first number of processor cycles between receiving the first instruction and receiving the RSWI. |
申请公布号 |
US2016062797(A1) |
申请公布日期 |
2016.03.03 |
申请号 |
US201414468969 |
申请日期 |
2014.08.26 |
申请人 |
Holt James C.;Kahne Brian C.;Moyer William C. |
发明人 |
Holt James C.;Kahne Brian C.;Moyer William C. |
分类号 |
G06F9/48;G06F9/38;G06F9/32;G06F9/46;G06F9/50 |
主分类号 |
G06F9/48 |
代理机构 |
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代理人 |
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主权项 |
1. A method comprising:
processing, by a processor core of a processing system, a first instruction of a first instance of a first basic block, wherein the first instruction of the first instance of the first basic block is a first-in-order instruction of the first instance of the first basic block; determining, by the processor core of the processing system, that a last-in-order instruction of the first instance of the first basic block is a resource switch instruction (RSWI); in response to determining that the last-in-order instruction of the first instance of the first basic block is the RSWI, storing, by the processor core of the processing system, a cycle count indicating a first number of processor cycles occurring between processing of the first instruction of the first instance of the first basic block and processing of the RSWI; processing, by the processor core of the processing system, a first instruction of a second instance of the first basic block; and initiating, by a hardware task scheduler of the processing system, a resource switch in response to processing the first instruction of the second instance of the first basic block, wherein the resource switch is initiated based on the cycle count. |
地址 |
Austin TX US |