HIGH DENSITY TRENCH-BASED POWER MOSFETS WITH SELF-ALIGNED ACTIVE CONTACTS AND METHOD FOR MAKING SUCH DEVICES

摘要

Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

主权项

1. A method of forming a MOSFET device comprising:
a) forming a hardmask over a top surface of a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate includes a lightly doped drift region formed in an upper portion of the substrate, wherein the hardmask includes first, second, and third insulator layers, wherein the second layer is sandwiched between the first and third layers, wherein the third layer is between the second layer and the top surface of the semiconductor substrate, and wherein the second layer is resistant to a first etch process that etches the material of the first and third layers, and wherein the first and third layers are resistant to a second etch process that etches the material of the second layer; b) etching the semiconductor substrate through openings in the hardmask to form a plurality of trenches in a semiconductor substrate; c) lining the trenches with an insulative layer ; d) disposing a conductive material in the trenches to form a plurality of gate electrodes; e) forming insulative gate caps above the gate electrodes up to at least a level of the second layer of the hardmask, wherein the insulative gate caps are made of a material that is etched by the first etch process and resistant to the second etch process; f) etching the first layer of the hardmask and the insulative gate caps down to a level of the second layer of the hardmask using the first etch process and removing the second layer of the hardmask using the second etch process, leaving insulative gate caps aligned with the trenches protruding above a level of the third layer of the hardmask; g) forming a body layer in a top portion of the substrate, wherein the body layer is a second conductivity type that is opposite of the first conductivity type; h) forming a source layer of the first conductivity type in a top portion of the body layer; i) forming a first insulative spacer layer over the gate caps and exposed portions of the third layer of the hardmask, and anisotropically etching the first insulative spacer layer leaving portions of the first insulative spacer layer along sidewalls of the insulative gate caps as first insulative spacers; j) forming a second insulative spacer layer over exposed portions of the third hardmask layer, the insulative gate caps and the first insulative spacers and anisotropically etching the second insulative spacer layer leaving a portion of the second insulative spacer layer along exposed sidewalls of the first insulative spacer as second insulative spacers,; and k) forming contact openings into the semiconductor substrate for source contacts using the first and second insulative spacers as a self-aligning mask.