EVENT CONTROLLED DECODING CIRCUIT

摘要

A waveform generator circuit includes a memory with address locations storing output waveform defining data bits. An address counter generates an address for sequentially addressing the address locations in the memory. The memory responds by sequentially outputting the output waveform defining data bits at the addressed locations. An output circuit receives the waveform defining data bits output from the memory and operates to generate an output signal waveform having logic state values dependent on the sequentially output waveform defining data bits.

主权项

1. A circuit, comprising:
an output circuit configured to receive data bits and generate an output signal waveform having logic state values dependent on the received data bits; a time counter configured to increment in response to a clock signal; a memory having a plurality of address locations, each address location storing a signal transition time linked to said data bits for that signal transition time, said memory outputting the data bits when the address location is addressed; a comparator configured to compare a counter value output from the time counter to the signal transition times stored in said memory and generate an increment signal in response to each comparison match; and an address counter configured to generate an address for addressing said address locations in the memory, said address counter incrementing the address in response to the increment signal at each instance of a comparison match.