MEMORY WITH LOCAL-/GLOBAL BIT LINE ARCHITECTURE AND ADDITIONAL CAPACITANCE FOR GLOBAL BIT LINE DISCHARGE IN READING

摘要

There is provided a memory unit comprising one or more global bit lines connected to a sense amplifier, and a plurality of memory cells that are grouped into a plurality of memory cell groups, each memory cell group having one or more local bit lines operatively connected to each of the memory cells in the memory cell group. Each memory cell group is configured such that, when a memory cell of the memory cell group is being read, the one or more local bit lines of the memory cell group are provided as inputs to a logic circuit and are not connected to the global bit lines, the logic circuit being configured to cause a capacitance element to be connected to one of the one or more global bit lines in dependence upon the states of the one or more local bit lines of the memory cell group.

主权项

1. A memory unit comprising:
a) a plurality of memory cells, each memory cell being associated with a wordline, the plurality of memory cells being grouped into a plurality of memory cell groups; b) each memory cell group having one or more local bit lines operatively connected to each of the memory cells in the memory cell group for which access to the memory cell is controlled by the associated wordline; and c) one or more global bit lines connected to a sense amplifier, the sense amplifier being configured to determine a data value stored in the memory cell in dependence upon the states of the one or more global bit lines; wherein each memory cell group is configured such that when the memory cell of the memory cell group is being read the one or more local bit lines of the memory cell group are provided as inputs to a logic circuit and are not connected to the global bit lines, the logic circuit being configured to cause a capacitance element to be connected to one of the one or more global bit lines in dependence upon the states of the one or more local bit lines of the memory cell group.