SELECTABLE PHASE OR CYCLE JITTER DETECTOR

摘要

Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

主权项

1. An apparatus, comprising:
a clock generation circuit configured to generate a clock signal; and one or more jitter detection circuits configured to:
generate a launch clock dependent on the clock signal and a launch phase selection signal;generate a data signal dependent upon the launch clock;generate a capture clock dependent on the clock signal;generate a plurality of delayed signals dependent upon the data signal;capture a respective one of the plurality of delayed signals responsive to the capture clock to generate a plurality of captured signals; andidentify one or more delayed signals of the plurality of delayed signals that were incorrectly captured dependent upon the plurality of captured signals.